The present invention relates to digital circuits and, more particularly, to domino logic circuits. Still more particularly, the present invention relates to modified domino logic circuits with increased noise tolerances.
Domino logic circuits are well known to those of skill in the art. FIG. 1A schematically illustrates a generalized prior art domino logic circuit 100A which typically included: supply voltage VDD; P-channel transistor 122; logic block 110, with data input nodes IN1 to INN; inverter 130; N-channel transistor 105; and ground supply voltage VSS.
In generalized prior art domino logic circuit 100A, source 122S of P-channel transistor 122 was coupled to junction 181 and supply voltage VDD. Gate 122G of P-channel transistor 122 was connected to node 142 which received clock signal CK. Drain 122D of P-channel transistor 122 was connected to junction 183. Node 183 was connected to a first internal node 190 and node 111 of logic block 110. First internal node 190 was also connected to input node 132 of inverter 130. Inverter 130 included output node 133 that was coupled to circuit output node 135.
Logic block 110 typically comprised one of several different logic circuits and/or gates well known to those of skill in the art. For instance, in one embodiment, logic block 110 comprised AND gate logic. However, logic block 110 could also comprise a NAND gate, OR gate, NOR gate, selective OR gate or any other gate or logic circuit required for a particular application of generalized prior art domino logic circuit 100A. Input nodes IN1 to INN of logic block 110 were connected to receive data signals D1 to DN. The number of data signals xe2x80x9cDNxe2x80x9d, and therefore the number in input nodes xe2x80x9cINNxe2x80x9d varied depending on the logic making up a particular embodiment of logic block 110 and the requirements of the system (not shown) employing prior art domino logic circuit 100A. A specific embodiment of logic block 110 is discussed in more detail below.
Logic block 110 also included node 112 that was connected to a second internal node 187. Second internal node 187 was connected to drain 105D of N-channel transistor 105. Gate 105G of N-channel transistor 105 was connected to input node 144 to receive the clock signal CK. Source 105S of N-channel transistor 105 was then connected to junction 189 and ground supply voltage VSS.
FIG. 1B schematically illustrates a prior art domino logic circuit 100B. Prior art domino logic circuit 100B is one of several possible embodiments of generalized prior art domino logic circuit 100A discussed above. Consequently, prior art domino logic circuit 100B is identical to generalized prior art logic circuit 100A but includes an AND gate embodiment of logic block 110 which comprises two data inputs, D1 and D2, and two N-channel transistors 101 and 103.
Prior art domino logic circuit 100B typically received two input data signals D1 and D2 at nodes 150 and 160, respectively. Prior art domino logic circuit 100B, like generalized prior art domino logic circuit 100A, also typically included P-channel transistor 122 and N-channel transistor 105.
As shown in FIG. 1B, N-channel transistors 101 and 103 were typically NMOS transistors having their channel regions connected in series between the drain 122D of P-channel transistor 122 at junction 183 and the drain 105D of N-channel transistor 105 at second internal node 187. More specifically, the source 122S of P-channel transistor 122 was connected to supply voltage VDD at junction 181 and the drain 122D of P-channel transistor 122 was connected to junction 183, first internal node 190, and input node 132 of inverter 130. Inverter 130 also included output node 133 connected to circuit output node 135.
N-channel transistor 101 typically had its drain 101D connected to junction 183 that, as discussed above, was connected to drain 122D of P-channel transistor 122, first internal node 190, and input node 132 of inverter 130. Source 101S of N-channel transistor 101 was connected to the drain 103D of N-channel transistor 103 at junction 185. The source 103S of N-channel transistor 103 was connected to drain 105D of N-channel transistor 105 at second internal node 187. The source 105S of N-channel transistor 105 was connected to ground supply voltage VSS at junction 189.
As with generalized prior art domino logic circuit 100A discussed above, in prior art domino logic circuit 100B, gate 122G of P-channel transistor 122 and gate 105G of N-channel transistor 105 were connected to nodes 142 and 144, respectively, to receive the clock signal CK. In addition, gate 101G of N-channel transistor 101 was connected to node 150 to receive data signal D1 and gate 103G of N-channel transistor 103 was connected to node 160 to receive data signal D2.
Particular types of transistors are discussed above, made by particular processes and with particular first or second channel types, i.e., xe2x80x9cPxe2x80x9d or xe2x80x9cNxe2x80x9d channel types. However, those of skill in the art will readily recognize that other types of transistors, made by other processes and/or having opposite first and second channel types, could be employed by making minor modifications such as changing the supply voltages VSS and VDD. The choice of the particular transistor types for the discussion above was made for exemplary purposes only. Therefore, this choice of transistor types should not be read as limiting the discussion of the prior art, or the invention, to the particular embodiments shown.
Disadvantageously, prior art domino logic circuits 101A and 100B were very sensitive, and therefore susceptible to, input noise levels on signals D1 to DN. Consequently, an input noise peak larger in magnitude than the threshold voltage of the evaluation device could, and often would, trigger domino logic circuit 100A or 100B and cause a logic malfunction. This was primarily because prior art domino logic circuits 100A and 100B did not use complementary logic so there was no buffer or xe2x80x9cfightxe2x80x9d with a complementary component during evaluation. Consequently, first internal node 190 of prior art domino logic circuits 100A and 100B started discharging as soon as the level of input signal D1 to DN went slightly above the threshold voltage of the pull down (or pull up) device, i.e., N-channel transistors 101 and 103 in FIG. 1B.
For instance, referring to FIG. 1B, assume data signal D1 at node 150 was high, i.e., a logic xe2x80x9c1xe2x80x9d, during evaluation, i.e., when clock signal CK was a high. In this case, first internal node 190 would start discharging when data signal D2 at node 160 reached the threshold voltage of N-channel transistor 103 (VTH103). Assuming that clock signal CK was high prior to signal D2 reaching VTH103, second internal node 187, i.e., source 103S of N-channel transistor 103 was at the same voltage as the ground supply voltage VSS. Therefore, the threshold voltage of N-channel transistor 103 was the threshold specified at zero bias voltage, i.e., VTH103, assuming no body effect. Consequently, prior art domino logic circuits 100A and 100B were very sensitive and susceptible to input noise levels and suffered from poor noise rejection characteristics and a low noise threshold.
Since prior art domino logic circuits 100A and 100B were so sensitive and susceptible to input noise levels, in prior art systems where input noise levels could not be reduced by other means static buffers were added to the inputs of dynamic domino logic circuits, such as prior art domino logic circuits 101A and 100B. The addition of these static buffers (not shown) created a static domino logic circuit (not shown) that was less vulnerable to noise. However, using this prior art buffer method, at least four additional devices (not shown) were required for each static buffer. Consequently, this method had a large penalty in terms of silicon area required to implement it and in speed. The speed penalty arose because each buffer added at least two (2) inverter delays.
What is needed is a method and structure to make a domino logic circuit that is less sensitive to input noise yet does not suffer large power and/or speed penalties.
According to the method and structure of the invention, a transistor is added to prior art domino logic circuits to create a modified domino logic circuit with a resistor divider connected between a first internal node and a second internal node. The resistor divider keeps the second internal node at a voltage that is greater than a second supply voltage at the beginning of the evaluation phase of the modified domino logic circuit. Consequently, a first internal node of the modified domino logic circuit will not start discharging until a greater voltage is reached by input signals. Thus, the input noise rejection of the modified domino logic circuit of the present invention is improved compared with prior art domino logic circuits.
In one embodiment of the invention, the modified domino logic circuit includes a first internal node and a second internal node. The first internal node is coupled to an output node of the modified domino logic circuit. A first transistor of a first channel type includes a first flow electrode, a second flow electrode and a control electrode. The first flow electrode of the first transistor is coupled to the second internal node of the modified domino logic circuit, the second flow electrode of the first transistor is coupled to a first supply voltage and the control electrode of the first transistor is coupled to the first internal node of the modified domino logic circuit. A second transistor of the first channel type includes a first flow electrode, a second flow electrode and a control electrode. The second flow electrode of the second transistor is coupled to the second internal node of the modified domino logic circuit, the first flow electrode of the second transistor is coupled a second supply voltage. As a result, the first and second transistors of the first channel type form a resistor divider coupled between the first internal node and the second internal node of the modified domino logic circuit.
In another embodiment of the invention, a first transistor of a second channel type includes a first flow electrode, a second flow electrode and a control electrode. The first flow electrode of the first transistor is coupled to a first supply voltage, the control electrode of the first transistor is coupled to receive a clock signal and the second flow electrode of the first transistor is coupled to a first internal node of the modified domino logic circuit. A logic block includes a first node, a second node, and at least one input node. The first node of the logic block is coupled to the first internal node of the modified domino logic circuit, the at least one input node of the logic block is coupled to receive at least one data signal and the second node of the logic block is coupled to a second internal node of the modified domino logic circuit. A second transistor of a first channel type includes a first flow electrode, a second flow electrode and a control electrode. The second flow electrode of the second transistor is coupled to the second internal node of the modified domino logic circuit, the control electrode of the second transistor is coupled to receive the clock signal and the first flow electrode of the second transistor is coupled to a second supply voltage. A third transistor of the first channel type includes a first flow electrode, a second flow electrode and a control electrode. The first flow electrode of the third transistor is coupled to the second internal node of the modified domino logic circuit, the second flow electrode of the third transistor is coupled to the first supply voltage and the control electrode of the third transistor is coupled to the first internal node of the modified domino logic circuit.
In yet another embodiment of the invention, a first transistor of a second channel type includes a first flow electrode, a second flow electrode and a control electrode. The first flow electrode of the first transistor is coupled to a first supply voltage, the control electrode of the first transistor is coupled to receive a clock signal and the second flow electrode of the first transistor is coupled to a first internal node of the modified domino logic circuit. A second transistor of a first channel type includes a first flow electrode, a second flow electrode and a control electrode. The second flow electrode of the second transistor is coupled to the second flow electrode of the first transistor and the control electrode of the second transistor is coupled to receive a first data signal. A third transistor of the first channel type includes a first flow electrode, a second flow electrode and a control electrode. The second flow electrode of the third transistor is coupled to the first flow electrode of the second transistor, the control electrode of the third transistor is coupled to receive a second data signal and the first flow electrode of the third transistor is coupled to a second internal node of the modified domino logic circuit. A fourth transistor of the first channel type includes a first flow electrode, a second flow electrode and a control electrode. The second flow electrode of the fourth transistor is coupled to the second internal node of the modified domino logic circuit, the control electrode of the fourth transistor is coupled to receive the clock signal and the first flow electrode of the fourth transistor is coupled to a second supply voltage. A fifth transistor of the first channel type includes a first flow electrode, a second flow electrode and a control electrode. The first flow electrode of the fifth transistor is coupled to the second internal node of the modified domino logic circuit, the second flow electrode of the fifth transistor is coupled to the first supply voltage and the control electrode of the fifth transistor is coupled to the first internal node of the modified domino logic circuit.
As described above, and in more detail below, in accordance with the present invention, an additional transistor of a first channel type is added to traditional prior art domino logic circuits, such as prior art domino logic circuits 100A and 100B discussed above. In one embodiment of the invention, a control electrode, e.g., the gate, of the added transistor is connected to a first internal node. The first internal node is connected to a second flow electrode, e.g., the drain, of a first transistor of a second channel type. The second flow electrode, e.g., the drain, of the added transistor and a first flow electrode, e.g., the source, of the first transistor of the second conductivity type are connected to a first supply voltage. The first flow electrode, e.g., the source, of the added transistor is connected to a second internal node which is positioned between a node of a logic block and a second flow electrode, e.g., the drain, of a second transistor of the first channel type. The first flow electrode, e.g., the source, of the second transistor of the first channel type is then connected to a second supply voltage.
In another embodiment of the invention: the gate of the added transistor of the first channel type is connected to a first internal node that is also connected to a drain of a first transistor of a second channel type and the drain of a first transistor of the first channel type; the drain of the added transistor of the first channel type and the source of the first transistor of the second channel type are connected to a first supply voltage; the source of the added transistor of the first channel type is connected to a second internal node which is also connected to the source of a second transistor of the first channel type and the drain of a third transistor of the first channel type; and the source of the third transistor of the first channel type is connected to a second supply voltage.
In one embodiment of the invention, the added transistor of the first channel type creates a resistor divider with another transistor of the first channel type. This resistor divider raises the voltage of the second internal node to a voltage that is greater than second supply voltage at the beginning of the evaluation phase of the modified domino logic circuit. Consequently, the input noise rejection of modified domino logic circuit is improved as discussed in more detail below.
A specific value for the voltage on the second internal node at the beginning of the evaluation phase can be obtained by selecting the appropriate channel width and length of for the transistors making up the resistor divider. Consequently, the input noise rejection of the modified domino logic circuit can be tailored to meet the specific needs of the designer.
The modified domino logic circuits of the invention are typically used in systems where input noise levels cannot be reduced by other means. In these cases, the solution of the present invention is more area efficient than the prior art method, discussed above, of adding static buffers to the inputs of a dynamic domino logic circuit to create a static domino logic circuit. This is because, using the method and structure of the invention, only one additional device is required, the added transistor. In contrast, using prior art methods, at least four additional devices were required for each static buffer.
In addition, the method and structure of the invention is more speed efficient than the prior art method of adding static buffers. This is because, as discussed in more detail below, each buffer required by prior art methods added at least two (2) inverter delays while, using the method of the invention, only one-half (xc2xd) of an inverter delay is added.
In addition, the method and structure of the invention is economical to implement using existing methods and devices. For instance, the additional transistor required by the invention can be added, but not connected, to the layout of critical domino logic circuit cells. Then, using the method and structure of the invention, the additional transistor of the invention can be left unconnected in the system until such time as it is accurately ascertained that the noise levels of the received signals warrant the minor speed and power penalties associated with the present invention discussed in more detail below. When a need is determined, the additional transistor can be connected with a mere change in the metal layer of the chip. Consequently, using the method and structure of the invention, even the minor speed and power penalties associated with the adding a single transistor can be avoided until it is determined accurately that a need exists.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.